DS1004Z-5 Five-Tap Delay Line For Timing Alignment

DS1004Z-5 is used when you need deterministic, hardware-based edge timing to align signals across logic paths. In fast digital designs, small skew can break setup and hold margins; DS1004Z-5 provides repeatable multi-tap delays so you can trim timing without reworking the clock tree. This part is a five-tap silicon delay line with a minimum 5ns input-to-tap1 delay, and the nominal tap delays for DS1004Z-5 are 5ns, 10ns, 15ns, 20ns, and 25ns. The datasheet specifies a 1.5ns nominal input-to-tap tolerance and a 1.0ns nominal tap-to-tap tolerance for the DS1004Z-5 option. Use DS1004Z-5 in timing alignment, pulse shaping, and interface delay compensation where fixed delays are preferred over programmable elements. Request a quote for DS1004Z-5.